The present disclosure relates generally to semiconductor device manufacturing, and more particularly to the fabrication methods of thin film transistors used in electro-optical display devices, sensors, and the like.
The manufacture of semiconductor integrated circuits (ICs) and devices require the use of many photolithography process steps to define and create specific circuit components and circuit layouts onto an underlying substrate. Conventional photolithography systems project specific circuit and/or component images, defined by a mask pattern reticle, onto a flat substrate coated with a light sensitive film (photoresist) coating. After image exposure, the film is then developed leaving the printed image of the circuit and/or component on the substrate. The imaged substrate is subsequently processed with techniques such as etching and doping to alter the substrate with the transferred pattern. Photolithography processes are used multiple times during the fabrication of thin film transistors (TFTs) that are used in electro-optical display devices and sensors.
Each photolithography process sequence represents invested fabrication costs to the final cost of the completed device. Such fabrication costs include all costs related to materials, labor, facilities, production yield losses and the time spent in the production state. Any process flow simplification that provides a reduction in any of the above mentioned cost areas will provide a net improvement to the final cost of fabricating the device. It is highly desirable to create and implement new process flows that feature process simplifications to lower fabrication costs. The reduction of photolithography process sequences represents a form of process simplification. Such process simplification will provide significant cost improvement for a given production facility to maintain highly competitive cost and output advantages over other manufacturers of similar product devices.
Referring now to FIGS. 1A through 1J, there are cross-sectional views of the production process sequences of a conventional p-channel thin film transistor (P-TFT) utilizing six photolithography masks. FIG. 1A shows a flat glass substrate 102 initially processed to obtain two additional films stacked upon the substrate surface. A buffer layer 104, usually comprised of an insulating material such as silicon oxide, is either deposited using chemical vapor deposition, or thermally grown in a gaseous environment. A poly-silicon layer 106 is then deposited upon the glass-buffer layer stack. The poly-silicon layer 106 is usually deposited using chemical vapor deposition and may be lightly doped during the deposition process with either n-type or p-type dopants. The optional doping of the poly-silicon layer 106 allows for the adjustment of the TFTs' voltage threshold characteristics along the transistor electrical gate channel that is defined during subsequent steps. It is noted that some conventional flows may use amorphous silicon as the material layer instead of the poly-crystalline silicon layer 106 used in this description.
The first photolithographic mask pattern 108 is placed on top of the poly-silicon 106, buffer 104; glass substrate 102 stack as shown in FIG. 1B. The mask pattern 108 is used to pattern the poly-silicon regions 106 where transistors will be located on the buffer layer 104 and substrate 102. The poly-silicon regions 106 under the mask pattern 108 are blocked from the poly-silicon etching process, thus forming segregated poly-silicon areas 106 as shown in FIG. 1C, that will subsequently become the base for an individual TFT device or simply TFT. A dielectric layer 110 such as silicon oxide is then either thermally grown in a gaseous environment or deposited by chemical vapor deposition on top of the exposed poly-silicon 106 and buffer 104 areas, as shown in FIG. 1D. This dielectric layer 110 is also known as the gate oxide layer, later serving as the gate dielectric of the TFT. FIG. 1D also shows the next layer, the gate metal layer 112, deposited on top of the gate oxide layer 110. The gate metal layer 112 is usually deposited upon the gate oxide 110 surface by ion sputtering of a metal source or by a chemical electrolysis process.
FIG. 1E shows the second photolithography mask pattern 114 situated on top of the gate metal layer 112. This mask pattern 114 allows for the etching-off of selected gate metal areas to create the TFT gate electrodes, as well as gate metal lines horizontal to the substrate 102 plane to connect selected multiple TFT gates forming specific circuit paths. The gate metal etch is usually performed using wet chemistries and may be supplemented with a dry chemical plasma etch.
FIG. 1F illustrates the view of the gate electrode 112 after the etching of the gate metal layer and after the removal of the mask pattern 114. After the removal of the mask pattern 114, the poly-silicon regions 118 and 120 adjacent to but not directly under the gate electrode 112 are doped with a p-type dopant. This doping process, usually accomplished by ion implantation 116 of p-type dopants such as boron or boron-difluoride, creates the TFTs' P+ source 118 and drain 120 regions within the poly-silicon area 106. It is noted that the poly-silicon region 106 located directly under the gate region, not doped by the doping process becomes the TFTs' electrical gate channel. The active TFT components, source 118, drain 120, gate 112 and transistor channel regions are now complete. It is also noted that the ion implantation process 116 is calibrated such that dopant placement is primarily located within the poly-silicon regions 118 and 120 and the gate metal 112 blocks the doping of the transistor gate channel. For the fabrication of n-channel TFT structures, the source/drain ion implantation 116 will utilize n-type dopants such as phosphorus to create N+ source and drain regions. A thermal anneal process (not shown in the attached figures) is usually performed after the source, drain doping process to repair any physical damage to the doped layers, as well as to activate and distribute the added dopants.
FIG. 1G illustrates the cross-sectional view of the TFT device after processing through the third mask. The figure shows an interlevel dielectric (ILD) layer 122 that has been deposited on top of the gate metal 112. The ILD layer 122 has been patterned and etched to create selected areas of vertical openings 124 from the top surface of the ILD layer 122 down to expose the TFT source 118 and drain 120 regions. The ILD layer 122 is usually created by a chemical deposition process and etched using a wet chemical and/or dry chemical plasma process. The vertical openings 124 are then lined and filled with conductive metal(s), usually by ion sputtering, to provide a vertical interconnection path from the top of the ILD layer 122 to the TFTs' source 118 and drain 120 regions.
After the creation of the filled vertical interconnections, a new blanket metal layer 126 is then deposited upon the ILD layer 122. This metal layer 126 is usually created by ion sputtering of a metal source or by a chemical electrolysis process. The fourth mask (not shown) is then placed on top of the metal layer 126, used to define and create the horizontal metal lines connecting selected source 118 and drain 120 regions of selected TFTs to form a desired circuit. FIG. 1H shows the cross-sectional view of the TFT device after the fourth mask pattern has been applied and the metal pattern etched. The new metal lines 126 on top of the ILD layer 122 are shown connected to the TFT source 118 and drain 120 regions through the previously created and filled vertical interconnects 124. After the formation of the metal lines 126, a passivation dielectric layer 128 is then deposited on top of the TFT device.
FIG. 1I shows the cross-sectional view of the TFT device after using the fifth mask. The fifth mask pattern has been placed on top of the passivation layer 128 and used to selectively etch off certain regions of the layer to expose a vertical interconnect path opening 130 to the last-placed metal lines 126. The etched openings 130 are vertical interconnection paths to connect the last-placed (source and drain) metal lines 126 to the next metal lines that will be created on the top surface of the passivation layer 128. The passivation dielectric layer 128 is usually created by a chemical deposition process and etched using a wet chemical and/or dry chemical plasma process. The vertical openings 130 are lined and filled with conductive metal(s), usually by ion sputtering.
After the vertical interconnection openings 130 are lined and filled with conductive metal(s), a final routing metal layer 132 is deposited upon the surface of the passivation layer 128. This final metal layer 132, usually comprised of indium tin oxide (ITO), is then patterned using the sixth and final mask pattern to create the circuit paths for final routing of the TFTs' source 118 and drain 120 regions. FIG. 1J illustrates this showing the filled vertical interconnection openings 130 and the etched ITO metal lines 132. After the completion of this sixth mask processing, the basic TFT device is completed.
It is again noted any process flow simplification that provides a reduction in any of the above mentioned process operations will provide a net improvement to the final cost of fabricating the device.
What is desirable is an improved process flows that feature process simplifications to lower fabrication costs while maintaining the required physical and electrical performance characteristics of the semiconductor device and components.